The present invention relates to generation of signals, and more particularly to generation of signals from other signals that take time to develop on power-up.
Some circuits develop signals not from signals immediately available on power-up, e.g. from an external power supply voltage, but from other signals that take time to develop during power-up, e.g. from an internal power supply voltage. One reason for using an internal power supply may be a desire to be able to use the same circuit with different external power supply voltages. Consider, for example, a semiconductor memory in which a substrate or a well is biased by a bias voltage selected to reduce transistor leakage current or to adjust transistor threshold voltages or junction capacitances. The bias voltage generator has to generate the correct bias voltages for different external power supply voltages. Bias voltage generation could be simplified if the bias voltage could be generated from an internal power supply voltage independent of the external power supply voltage level. However, the internal power supply voltage takes time to develop on power-up, which causes problems described below in connection with FIG. 2.
FIG. 1 illustrates a bias voltage generator 110 generating a bias voltage VBB from an external power supply voltage EVCC in a dynamic random access memory (DRAM). VBB is a negative voltage which biases the P substrate or P wells in which the NMOS transistors of DRAM cells are fabricated. The possible nominal EVCC values are 3.3V and 5.0V. However, the 5.0V EVCC could subject the transistors to high stresses. To avoid these stresses, the circuitry that drives the transistors uses an internally generated power supply voltage IVCC. IVCC is generated from EVCC so that IVCC is about 3.0V for either 3.3V or 5.0V EVCC values. Since IVCC is the same for different EVCC values, and since the DRAM cell transistors are driven by IVCC, VBB can be the same for different EVCC values. (In FIG. 1, VBB is about -1.5V.)
To generate the same VBB from different EVCC voltages, VBB generator 110 uses a fuse F1. When fuse F1 is intact, fuse F1 shunts the resistor R3 connected in parallel with the fuse. The resistor R3 is connected in series with resistors R2 and R1 between VBB and EVCC. If the memory is to operate at EVCC=3.3V, the fuse is blown. If the memory is to operate at EVCC=5.0V, the fuse is left intact. The resistors R1, R2, R3 are selected so that when VBB is at the desired value of -1.5V, the node 120 between the resistors R1 and R2 is at half EVCC (that is, 1.65V when EVCC=3.3V and the fuse is blown; 2.5V when EVCC=5.0V and the fuse is intact). Half EVCC is the trip voltage of CMOS inverter 124 whose input is connected to node 120. (The letter E inside the inverter symbol means that the inverter is powered by EVCC. The reference voltage is assumed ground unless mentioned otherwise.) Inverters 124, 130, 134, 138 are connected in series between node 120 and charge pump 140. These inverters are powered by EVCC. The output of inverter 138 provides the charge pump enable signal VBE. The charge pump is on when VBE is high. The charge pump is off when VBE is low. Thus, when VBB rises above -1.5V, the charge pump turns on. When VBB falls to -1.5V, the charge pump turns off.
Some embodiments use a mask option instead of fuse F1.
To eliminate the fuse or the mask option, some DRAMs generate the bias voltage VBB from IVCC because IVCC has the same value for different EVCC levels. See VBB generator 210 in FIG. 2. In VBB generator 210, resistors R4 and R5 are connected in series between IVCC and VBB. Node 120 between the resistors R4 and R5 is connected to the input of inverter 214 powered by IVCC. The output of inverter 214 is connected to the input on inverter 218 also powered by IVCC. The output signal IntEn of inverter 218 is provided to the charge pump (not shown) as the enable signal VBE. The resistors R4 and R5 are selected so that when VBB is at the desired value of -1.5V, node 120 is at the trip voltage of inverter 214. The trip voltage is one-half of IVCC, that is, 1.5V.
Bias voltage generator 210 has the following disadvantages associated with power-up. Since the internal voltage IVCC is used by many circuits in the memory, the IVCC terminal has a fairly large capacitance. Therefore, on power-up, a large amount of time elapses before IVCC develops. Another reason why IVCC is slow to develop is the use of low-power, slow circuitry for IVCC generation. The circuitry is made slow to reduce its DC power consumption. Because IVCC is slow to develop, IntEn does not enable the charge pump until long after the power has been turned on. During that period of time, the potential of the substrate or P wells biased by VBB could become positive, causing a latch-up.
One solution of this problem is to use the inverse of IntEn, i.e. the signal IntEn-, to control the charge pump. (IntEn- is generated from IntEn by inverter 230 powered by IVCC.) In such a circuit, the charge pump is turned on when IntEn- is low. The circuitry (not shown) detecting the level of IntEn-, and the charge pump, are driven by EVCC. Therefore, this circuitry and the charge pump become fully operational right away, before IVCC develops. When the power is first turned on, IntEn- is low, and hence the charge pump turns on right away. However, the charge pump will not turn off until IVCC develops, because IntEn- will be low until IVCC develops. By the time the pump turns off, VBB could become too low, for example, about -3V or -4V. Such low VBB values could increase the current leakage across pn-junctions in the wells or substrate biased by VBB. The memory cells could get discharged, losing information.
Therefore, there is a need for an improved generator of bias voltages and other signals that are generated from signals which take time to develop on power-up.